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All Technical Committee Conferences (Searched in: All Years)
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| Search Results: Conference Papers |
| Conference Papers (Available on Advance Programs) (Sort by: Date Descending) |
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| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| IST |
2026-03-27
13:10 |
Tokyo |
Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online) |
Silicon-on-Insulator Pixel FinFET Technology for a High Conversion Gain and Low Dark Noise 2-Layer Transistor Pixel Stacked CIS
Ryohei Takayanagi, Takashi Kamo, Ryosuke Yamachi, Mayu Sakurai, Hidetoshi Oishi, Takuya Iriguchi, Hiroshi Takahashi, Taikei Enomoto, Yuki Kageyama, Yusuke Tanaka, Yoshiaki Kikuchi, Junpei Yamamoto, hideomi kumano, Shinichi Yoshida, Yoshiaki Kitano, Kazunobu Ohta, Tomoyuki Hirano (Sony Semiconductor Solutions) |
This study presents a 2-Layer transistor pixel stacked 0.8-µm dual-pixel (DP) CIS with silicon-on-insulator (SOI) fin fi... [more] |
IST2026-19
pp.40-43 |
| IST |
2025-03-21
14:35 |
Tokyo |
Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online) |
Low Dark Noise and 8.5k e- Full Well Capacity in a 2-Layer Transistor Stacked 0.8μm Dual Pixel CIS with Intermediate Poly-Si Wiring
Yosuke Satake, Shinya Sato, Masayuki Takase, Mizuki Hoyano, Shuhei Kasukawa, Yusuke Tanaka, Yoshiaki Kitano, Manabu Tomita, Junpei Yamamoto, Kai Tokuhiro, Yoshiaki Kikuchi, Hirano Tomoyuki, Yoshiki Nishida (SSS) |
[more] |
IST2025-17
pp.32-36 |
| IST |
2022-09-22
13:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online) |
A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency
Chihiro Tomita, Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yusuke Satake (SSS), Takashi Watanabe, Kunihiko Araki, Naoki Nei (SCK), Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara (SSS), Hiroyuki Kawashima, Yusaku Kobayashi (SCK), Tomoyuki Hirano, Keiji Tatani (SSS) |
[more] |
IST2022-34
pp.1-4 |
| IEICE-ICD, IEICE-SDM, IST [detail] |
2022-08-08
09:00 |
Online |
On-line |
[Invited Talk]
A 2-Layer Transistor Pixel Stacked CMOS Image Sensor with Oxide Based Full Trench Isolation for Large Full Well Capacity and High Quantum Efficiency
Koichiro Zaitsu, Akira Matsumoto, Mizuki Nishida, Yusuke Tanaka, Hirofumi Yamashita, Yosuke Satake (Sony Semiconductor Solutions), Takashi Watanabe, Kunihiko Araki, Naoki Nei (Sony Semiconductor Manufacturing), Keiichi Nakazawa, Junpei Yamamoto, Mutsuo Uehara (Sony Semiconductor Solutions), Hiroyuki Kawashima, Yusaku Kobayashi (Sony Semiconductor Manufacturing), Tomoyuki Hirano, Keiji Tatani (Sony Semiconductor Solutions) |
[more] |
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| IST, CE |
2012-03-30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg. |
Extremely-Low-Noise CMOS Image Sensor with High Saturation Capacity
Kazuichiroh Itonaga, Kyohei Mizuta, Toyotaka Kataoka, Harumi Ikeda, Masashii Yanagita, Hiroaki Ishiwata, Yusuke Tanaka, Takashi Wakano, Yoshihisa Matoba, Tetsuya Oishi, Ryou Yamamoto, Shinichi Arakawa, Jun Komachi, Mikio Katsumata, Shinya Watanabe (Sony) |
We have developed a flat device structure, which we call “FLAT”, with no isolation grooves/ridges and no Si substrate et... [more] |
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IEICE-OCS, IEICE-OFT, BCT, IEE-CMN
(Joint) [detail] |
2011-11-18
11:50 |
Shimane |
Shimane Univ. |
A study on high-capacity and long-reach 10Gbps TDM-PON with OCDMA technology
Satoshi Yoshima (Mitsubishi Electric), Yusuke Tanaka (Osaka Univ.), Nobuyuki Kataoka (NICT), Junichi Nakagawa (Mitsubishi Electric), Naoya Wada (NICT), Ken-ichi Kitayama (Osaka Univ.) |
(Advance abstract in Japanese is available) [more] |
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