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Committee Date Time Place Paper Title / Authors Abstract Paper #
IST 2025-03-21
14:35		 Tokyo Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online)		 Low Dark Noise and 8.5k e- Full Well Capacity in a 2-Layer Transistor Stacked 0.8μm Dual Pixel CIS with Intermediate Poly-Si Wiring
Yosuke Satake, Shinya Sato, Masayuki Takase, Mizuki Hoyano, Shuhei Kasukawa, Yusuke Tanaka, Yoshiaki Kitano, Manabu Tomita, Junpei Yamamoto, Kai Tokuhiro, Yoshiaki Kikuchi, Hirano Tomoyuki, Yoshiki Nishida (SSS) 		 [more] IST2025-17
pp.32-36
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