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| Committee |
Date Time |
Place |
Paper Title / Authors |
Abstract |
Paper # |
| IST |
2023-09-15
14:30 |
Tokyo |
Kikai-Shinko-Kaikan Bldg.
(Primary: On-site, Secondary: Online) |
High Full Well Capacity and Low Noise Characteristics in 0.6 μm Pixels via Buried Sublocal Connections in a 2-Layer Transistor Pixel Stacked CMOS Imager Sensor
Keiji Nishida, Masataka Sugimoto, Tatsuya Okawa, Kanta Suzuki, Tomoharu Ogita, Katsunori Hiramatsu, Tomoyuki Hirano, Yoshiaki Kikuchi (SSS), Yuji Nishimura, Kohei Takeuchi, Daisuke Yoneyama, Toru Nagaki, Noriteru Yamada, Hiroyuki Kawashima (SCK), Yoshiaki Kitano (SSS) |
[more] |
IST2023-42
pp.29-32 |
| IST |
2022-03-28
09:55 |
Online |
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3D Sequential Process Integraton for CMOS Image Sensor
Keiichi Nakazawa, Junpei Yamamoto, Shigetaka Mori, Shintarou Okamoto, Akito Shimizu, Koichi Baba, Nobutoshi Fujii, Mutsuo Uehara, Katsunori Hiramatsu, Hideomi Kumano, Akira Matsumoto, Kouichirou Zaitsu, Hidetoshi Ohnuma, Keiji Tatani, Tomoyuki Hirano, Hayato Iwamoto (Sony Semconductor Solutions Corp.) |
We developed a new structure of pixel transistors stacked over photodiode named “2-Layer Transistor Pixel Stacked CMOS I... [more] |
IST2022-12
pp.9-12 |
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