| Paper Abstract and Keywords |
| Presentation |
2025-03-21 14:35
Low Dark Noise and 8.5k e- Full Well Capacity in a 2-Layer Transistor Stacked 0.8μm Dual Pixel CIS with Intermediate Poly-Si Wiring Yosuke Satake, Shinya Sato, Masayuki Takase, Mizuki Hoyano, Shuhei Kasukawa, Yusuke Tanaka, Yoshiaki Kitano, Manabu Tomita, Junpei Yamamoto, Kai Tokuhiro, Yoshiaki Kikuchi, Hirano Tomoyuki, Yoshiki Nishida (SSS) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
(Not available yet) |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
/ / / / / / / |
| Reference Info. |
ITE Tech. Rep., vol. 49, no. 13, IST2025-17, pp. 32-36, March 2025. |
| Paper # |
IST2025-17 |
| Date of Issue |
2025-03-14 (IST) |
| ISSN |
Online edition: ISSN 2424-1970 |
| Download PDF |
|