| Paper Abstract and Keywords |
| Presentation |
2025-03-21 14:10
A 2.1-ns Dead Time 5-μm Single Photon Avalanche Diode with 2-layer Transistor Pixel Technology
Shota Kitamura, Jun Ogi, Fumitaka Sugaya, Junki Suzuki, Aoi Magori, Tomonori Matsui, Kei Sumita, Yuki Ushiku (Sony Semiconductor Solutions), Koji Moriyama, Kenji Toshima (Sony Semiconductor Manufacturing), Tomohiro Namise, Hideki Ozawa, Yasunori Tsukuda, Yusuke Otake, Hiroki Hiyama, Shizunori Matsumoto, Atsushi Suzuki, Fumihiko Koga (Sony Semiconductor Solutions) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This study reports a 5-$mu$m-pitch single photon avalanche diode (SPAD) with 2-layer transistor pixel technology. The dead time is reduced to 2.1 ns, which is 1/3 times smaller than conventional three-dimensional-stacked SPAD pixels because the 2-layer pixel technology contributes to a reduced cathode capacitance by moving a pixel front-end circuit from the bottom tier logic chip to the 2nd layer of the top tier pixel chip. Simultaneously, the in-pixel counter for photon counting with time-of-flight imaging function increases from 5 to 7 bits. The dark count rate and photon detection efficiency at 940 nm and room temperature are 5.0 cps and 24.4 %, respectively. We maintained the characteristics comparable to the state-of-the-art SPAD pixels even with the 2-layer pixel technology. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
single photon avalanche diode / 2-layer transistor pixel technology / pixel front-end circuit / in-pixel counter circuit / dead time / photon detection efficiency / dark count rate / |
| Reference Info. |
ITE Tech. Rep., vol. 49, no. 13, IST2025-16, pp. 27-31, March 2025. |
| Paper # |
IST2025-16 |
| Date of Issue |
2025-03-14 (IST) |
| ISSN |
Online edition: ISSN 2424-1970 |
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