| Paper Abstract and Keywords |
| Presentation |
2024-08-05 11:25
Performance Enhancement and Design Optimization of Analog-to-Digital Converters Utilizing Dynamic Logics
Yuhao Xu, Ritaro Takenaka, Shuowei Li, Haoming Zhang, Tetsuya Iizuka (UTokyo) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
This paper presents a study on performance optimization techniques for SAR ADC by addressing the bottlenecks in speed performance caused by internal logic circuits. Specifically, this study identifies the critical path in digital control circuits designed with static logic and optimizes speed and power consumption performance by replacing circuits in the path with faster dynamic logic circuits. Using a 10-bit SAR ADC designed in a 28nm CMOS process as an example, two designs are analyzed based on static logic and demonstrate performance improvements through the substitution with dynamic logic circuits. Circuit simulations showed that the maximum sampling frequencies of ADCs can be increased from 513 MHz to 571 MHz and from 625 MHz to 690 MHz by utilizing two types of logic circuits respectively. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
SAR ADC / Dynamic Logic Circuits / Asynchronous Loop / / / / / |
| Reference Info. |
ITE Tech. Rep. |
| Paper # |
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| Date of Issue |
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| ISSN |
Online edition: ISSN 2424-1970 |
| Download PDF |
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| Conference Information |
| Committee |
IEICE-ICD IEICE-SDM IST |
| Conference Date |
2024-08-05 - 2024-08-07 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Analog, Mixed Analog and Digital, RF, and Sensor Interface, Low Voltage/Low Power Techniques, Novel Devices/Circuits, and the Applications |
| Paper Information |
| Registration To |
IEICE-ICD |
| Conference Code |
2024-08-SDM-ICD-IST |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Performance Enhancement and Design Optimization of Analog-to-Digital Converters Utilizing Dynamic Logics |
| Sub Title (in English) |
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| Keyword(1) |
SAR ADC |
| Keyword(2) |
Dynamic Logic Circuits |
| Keyword(3) |
Asynchronous Loop |
| Keyword(4) |
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| Keyword(5) |
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| 1st Author's Name |
Yuhao Xu |
| 1st Author's Affiliation |
The University of Tokyo (UTokyo) |
| 2nd Author's Name |
Ritaro Takenaka |
| 2nd Author's Affiliation |
The University of Tokyo (UTokyo) |
| 3rd Author's Name |
Shuowei Li |
| 3rd Author's Affiliation |
The University of Tokyo (UTokyo) |
| 4th Author's Name |
Haoming Zhang |
| 4th Author's Affiliation |
The University of Tokyo (UTokyo) |
| 5th Author's Name |
Tetsuya Iizuka |
| 5th Author's Affiliation |
The University of Tokyo (UTokyo) |
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| Speaker |
Author-1 |
| Date Time |
2024-08-05 11:25:00 |
| Presentation Time |
25 minutes |
| Registration for |
IEICE-ICD |
| Paper # |
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| Volume (vol) |
vol.48 |
| Number (no) |
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| Page |
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