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Paper Abstract and Keywords
Presentation 2012-12-06 15:00
Performance of Parallel Control Circuit for Benes Networks with Optimized VHDL Description
Hiedya Ichimura, Yousuke Kato, Hitoshi Obara (Akita Univ.)
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(in English) (Not available yet)
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Conference Information
Committee BCT IPSJ-AVM IEICE-CS IEICE-IE  
Conference Date 2012-12-06 - 2012-12-07 
Place (in Japanese) (See Japanese page) 
Place (in English) Fukuisi-chiiki-kouryu-plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Image Conding, Streaming, etc. 
Paper Information
Registration To IEICE-CS 
Conference Code 2012-12-BCT-AVM-CS-IE 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance of Parallel Control Circuit for Benes Networks with Optimized VHDL Description 
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1st Author's Name Hiedya Ichimura  
1st Author's Affiliation Akita University (Akita Univ.)
2nd Author's Name Yousuke Kato  
2nd Author's Affiliation Akita University (Akita Univ.)
3rd Author's Name Hitoshi Obara  
3rd Author's Affiliation Akita University (Akita Univ.)
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Date Time 2012-12-06 15:00:00 
Presentation Time 20 minutes 
Registration for IEICE-CS 
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Volume (vol) vol.36 
Number (no) no.53 
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