| Conference Information |
| Committee |
IST IEICE-ICD |
| Conference Date |
2012-07-26 - 2012-07-27 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Yamagata University (Yonezawa) |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
Analog, Mixed analog and digital, RF, and sensor interface circuitry |
| Paper Information |
| Registration To |
IEICE-ICD |
| Conference Code |
2012-07-ICD-IST |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Loop Design Optimization for Fourth-Order Fractional-N PLL Frequency Synthesizers |
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| 1st Author's Name |
Shoichi Masui |
| 1st Author's Affiliation |
Fujitsu Laboratories (Fujitsu Labs) |
| 2nd Author's Name |
Lee Jun-Gyu |
| 2nd Author's Affiliation |
Tohoku University (Tohoku Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2012-07-27 11:15:00 |
| Presentation Time |
25 minutes |
| Registration for |
IEICE-ICD |
| Paper # |
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| Volume (vol) |
vol.36 |
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